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Freescale Semiconductor Advance Information
Document Number: LP1071 Rev. 0.5, 12/2005
LP1071
802.11a/b/g Baseband System Solution
1
1.1
Introduction
The LP1070 Family
Contents
1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2 Specifications . . . . . . . . . . . . . . . . . . . . . . . . . 3 3 Functional Description . . . . . . . . . . . . . . . . . 4 4 LP1071 Interfaces . . . . . . . . . . . . . . . . . . . . . 10 5 Timers/Reset . . . . . . . . . . . . . . . . . . . . . . . . . 15 6 Pinout and Footprint . . . . . . . . . . . . . . . . . . 16 7 DC Electrical Specifications . . . . . . . . . . . . 22 8 Timing Characteristics . . . . . . . . . . . . . . . . . 25 9 Mechanical Dimensions . . . . . . . . . . . . . . . . 28 10 Development Support . . . . . . . . . . . . . . . . . 28 11 Appendix: Comparison of LP1071 and LP1072 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 12 Revision History . . . . . . . . . . . . . . . . . . . . . 30
Freescale Semiconductor's 802.11 LP1070 family consists of high-performance, highly optimized PHY and MAC baseband Wireless LAN processors that fully implement the IEEE 802.11a, 802.11b and 802.11g PHY standards. These baseband processors are poised to revolutionize the Wireless LAN industry by setting new standards for power consumption, size, cost and performance. The LP1070 family is based on Freescale's proprietary Wireless Broadband Signal ProcessorTM (WBSPTM), an innovative and revolutionary receiver architecture that significantly reduces size and power consumption while providing maximum flexibility to support multiple wireless standards with no additional overhead. In addition to their superior performance and ultra low power consumption, the LP1070 processors provide the customers with the flexibility to tailor the chip characteristics to their needs. With software control, the
This document contains information on a new product. Specifications and information herein are subject to change without notice. (c) Freescale Semiconductor, Inc., 2005. All rights reserved. PRELIMINARY
Introduction
terminal manufacturers can tune the chip performance to get the exact balance they opt for when it comes to power consumption and performance.
1.2
General Description
The high-performance LP1071 baseband processor integrates the IEEE 802.11a/b/g PHY and full MAC functionality with the industry's smallest package and the lowest power consumption compared to any baseband processor in the market. The LP1071 was designed to target embedded devices and small form factor SDIO WLAN devices. Its support for SDIO host interface combined with its ultra low power consumption and small size make it the optimal solution for mobile devices. It has been designed with a generic RF interface that lets it interface with virtually any RF components in the market. It has been fully tested to interface with RF solutions from Maxim and Airoha, thus providing terminal manufacturers with added flexibility in selecting the most appropriate RF parts based on their application and form factor. The LP1071's integrated ADC and DAC reduce the terminal manufacturers' bill of material and overall system cost. The integrated internal memory eliminates the need for external MAC memory, further reducing cost and saving valuable board space for small form factor devices. The LP1071 also provides the highest level of WLAN security by fully supporting WPA and AES.
1.3
* * * * * * * * * * * * * * * * * *
Feature Highlights
Full compliance with 802.11a/b/g Ultra low power consumption, maximizing battery life and minimizing heat dissipation Ultra small package: 9.0 x 9.0 x 1.0 (max) mm Fully embedded ARM7TDMI(R) microprocessor for no load on the host processor, leading to maximum flexibility in supporting different host platforms Implementations of 802.11e Draft, for support of Quality of Service (QoS) real-time applications 802.11i support, including WPA and AES, for enhanced security Automatic power management to reduce power consumption On-chip ADC and DAC to reduce system BOM and save on board area On-Chip PLL for clock generation On-chip ROM/RAM eliminating the need for external MAC memory Direct memory access (DMA) to reduce CPU utilization High throughput achieved using DMA Support of SDIO host interface Serial EEPROM interface for initialization and device booting Eight General Purpose I/O (GPIO) pins for added flexibility UART interface to support diagnostic tools and general data transfer JTAG Interface for testing and debugging Hardware engines for WEP, TKIP and AES support for less processor load
LP1071 Advance Information, Rev. 0.5 2 PRELIMINARY Freescale Semiconductor
Specifications
* * *
Supports Direct Conversion (Zero-IF) radio architecture, saving RF components thus reducing BOM cost and simplifying board layout Generic RF interface that lets it work with virtually an WLAN RF components. Currently fully tested with RF from Maxim and Airoha. Total Flexibility in meeting customer requirements by providing software-controlled trade-off between competing performance metrics.
2
Specifications
Table 1. Specifications
Feature Network Standard Support Network Architectures Data Rates IEEE 802.11a/b/g Infrastructure, AdHoc 802.11 a/g: 802.11b: Modulation Techniques Security Receiver Sensitivity 6, 9, 12, 18, 24, 36, 48, 54 Mbps 1, 2, 5.5, 11 Mbps Details
BPSK, QPSK, 16QAM, 64QAM, CCK, OFDM, DSSS 40- and 128-bit WEP, TKIP, WPA, AES 802.11g 6 Mbps: -91.0 dBm 9 Mbps: -90.5 dBm 12 Mbps: -88.6 dBm 18 Mbps: -86.4 dBm 24 Mbps: -81.4 dBm 36 Mbps: -79.9 dBm 48 Mbps: -76.1 dBm 54Mbps: -73.1 dBm 802.11b 1 Mbps: -97.4 dBm 2 Mbps: -94.1 dBm 5.5Mbps: -92.5 dBm 11Mbps: -88.9 dBm
Power Consumption
Receive: 150 mW avg (@54Mbps) Listen: Sleep: 132 mW Less than1 mW 3.3 0.3 Vdc 1.8 5% Vdc
Supply Voltage
I/O: Core:
Operating Temperature Host Interface Other Interfaces
0C to +70C; < 95% humidity SDIO, compliant with SDIO Card Specifications, Version 1.00 JTAG 8 GPIO pins One UART Serial EEPROM
Operating System Support
Microsoft Windows CE.net 3.0, 4.2, 5.0 Microsoft Pocket PC 2002, 2003
Packaging Options
144-pin VFBGA, 9.0 x 9.0 x 1.0 (max) mm
LP1071 Advance Information, Rev. 0.5 Freescale Semiconductor PRELIMINARY 3
Functional Description
Table 1. Specifications (continued)
Feature Semiconductor Technology RF Support Certification 0.18 micron Airoha, Maxim Wi-Fi(R) (incl. WPA), WQHL, FCC Part 15 Details
3
Functional Description
LP1071 Chip Boundary
On-Chip RAM/ROM
Figure 1 is a functional block diagram of the LP1071, which is divided into three main subsystems.
Shared Memory
ARM7TDMI
MAC Subsystem
Memory Controller Protocol Accelerator Subsystem ARM Interface WEP Engine Generic Host Interface Shared Memory Controller AHB AES Engine 802.11 Protocol Accelerator
AHB
ARM Subsystem
PHY Subsystem
AFE
AFE Control I/Q ADC I/Q DAC Aux ADC
AHB Bridge Watchdog Timer Interrupt Controller SDIO Registers Clock Control Clock Gating
ARM Interface MAC-PHY Interface WBSP
TM
UART JTAG EEPROM Interface GPIO RMB Registers APB+
Aux DAC SDIO Interface
Clock Select Logic
DMA
RSSI ADC
PLL
CLKIN
(From TCXO)
Figure 1. Functional Block Diagram
3.1
Embedded Processor Subsystem
The embedded Processor Subsystem consists of the following: * An embedded ARM7TDMI microprocessor running at 88 MHz * An ARM(R) Peripheral Subsystem accessed via an extended APB (APB+) bus
3.1.1
UART
The UART is used for testing and diagnostic purposes and is capable of supporting data transfer rates of up to 115.2 kbps.
LP1071 Advance Information, Rev. 0.5 4 PRELIMINARY Freescale Semiconductor
Functional Description
3.1.2
TBA
JTAG
3.1.3
Serial EEPROM Interface
The LP1071 supports an external serial EEPROM for storing the boot loader, MAC address, calibration data and any other vendor-specific data. The LP1071 supports serial EEPROMs of sizes from 8 Kbit (organized as 1024 entries of 8 bits each, or 1024 x 8) up to 512 Kbit (organized as 65,536 x 8). Serial EEPROMs from the following vendors have been tested and verified to work with the LP1071: * ATMEL (http://www.atmel.com) * ST Microelectronics (http://www.st.com) * Microchip Technology (http://www.microchip.com) * Catalyst Semiconductor (http://www.catsemi.com) * Integrated Silicon Solutions, Inc. (http://www.issi.com) The EEPROM is supported through GPIOs. There is no dedicated hardware to support either I2C or SPI serial EEPROMs. The operating frequency of the serial EEPROM port is 400 kHz with a supply voltage of 3.0 V.
3.1.4
GPIO
To support vendor-specific needs, the LP1071 provides eight bi-directional General Purpose Input Output (GPIO) pins. Each pin can be independently configured as an input, output or an interrupt source. On reset, the GPIOs default as inputs, i.e. output drivers enables will be inactive.
3.1.5
RMB Registers
This block contains all the reset logic for both CPUs contained in the BRC and chip-wide reset control. It also defines controls for memory address re-mapping.
3.1.6
TBA
Watchdog
3.1.7
TBA
Interrupt Controller
3.1.8
TBA
SDIO Registers
LP1071 Advance Information, Rev. 0.5 Freescale Semiconductor PRELIMINARY 5
Functional Description
3.1.9
TBA
Clock Control
3.1.10
Clock Gating
This block contains all the control logic required to gate individual sub-block clocks.
3.2
3.2.1
Media Access Control (MAC) Subsystem
Protocol Accelerator Subsystem (PAS)
The main function of the Protocol Accelerator Subsystem is to provide hardware acceleration functions for the MAC Software to perform the time critical aspects of the 802.11 protocol. The PAS contains the following: * * * * * Shared Memory Controller - provides arbitrated access to the shared memory (MAC memory) WEP Hardware Engine AES Hardware Engine 802.11 Protocol Accelerator - for support of time-critical MAC functions Generic Host Interface
3.2.2
AES Block
The contents of the AES block are: * AES encryption/decryption core that performs AES encryption/decryption of a 128-bit block. * Offset Codebook (OCB) mode encipher/decipher wrapper that performs OCB mode key generation for the AES core. * DMA controller and Shared Memory Interface that controls the reading/writing of data blocks from/to the PAS shared memory controller. * Control Registers, used to configure the operation of the AES block.
3.2.3
TBA
WEP Block
3.3
TBA
PHY Subsystem
LP1071 Advance Information, Rev. 0.5 6 PRELIMINARY Freescale Semiconductor
Functional Description
3.4
Analog Front End (AFE)
The Analog Front End (AFE) block consists of three Analog-to-Digital Converters (ADCs) and two Digital-to-Analog Converters (DACs) as given in Table 2.
Table 2. AFE Components
Component I/Q ADC I/Q DAC RSSI ADC Auxiliary ADC Auxiliary DAC Description A 2-channel ADC whose digital output serves as input to digital baseband and whose input is the differential signal from the RF (RX mode). A 2-channel DAC whose digital input is from baseband and output is a differential signal for the RF (TX mode). A single ended, single channel ADC A single ended, single channel ADC A single ended, single channel DAC Resolution 8-bit 8-bit 6-bit 8-bit 8-bit Clock 22 Msps 44 Msps 10 Msps 1 Msps 20 Msps
3.4.1
I/Q ADC
Table 3. I/Q ADC Specifications
Parameter Condition -- -- -- Fixed capacitance Switched capacitance @Fs Min -- 22 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- From Shutdown From Standby -1 -- -- Typ 8 -- 11 1 1 4 1.0 0.5 -48.5 -47 48.5 47 7.2 7.0 0.2 0.5 -- -- -- Max -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- +1 1 10 Units bit MHz MHz pF pF cycles LSB LSB dB dB dB dB bit bit dB Degree LSB ms s
I/Q ADC specifications are shown in Table 3.
Resolution Maximum Sampling Frequency Signal Bandwidth Input impedance
Latency Integral Nonlinearity (INL) Differential Nonlinearity (DNL) Total Harmonic Distortion (THD) Fin= 1MHz Fin= 10MHz SNR Fin= 1MHz Fin= 10MHz ENOB Fin= 1MHz Fin= 10MHz Channel-to-Channel mismatch Gain Phase DC offset after calibration Wake-up time
-- -- --
LP1071 Advance Information, Rev. 0.5 Freescale Semiconductor PRELIMINARY 7
Functional Description
3.4.2
I/Q DAC
Table 4. I/Q DAC
Parameter Condition -- -- -- -- -- -- -- Fin= 1MHz Fin= 10MHz Min -- 44 -- 0.7 10 5 -- -- -- -- -- -- -- -- -- -- -- From Shutdown From Standby -1 -- -- 1.0 0.5 -48.5 -47 48.5 47 7.2 7.0 0.2 0.5 -- -- -- -- -- -- -- -- -- -- -- -- -- +1 10 2 Typ 8 -- 11 Vcmo1 Max -- -- -- 1.5 Units bit MHz MHz V Kohm pF LSB LSB dB dB dB dB bit bit dB Degree LSB s s
I/Q DAC specifications are shown in Table 4.
Resolution Maximum Update rate 3dB Signal Bandwidth Output common-mode voltage Load Integral Nonlinearity (INL) Differential Nonlinearity (DNL) Total Harmonic Distortion (THD)
SNR
Fin= 1MHz Fin= 10MHz
ENOB
Fin= 1MHz Fin= 10MHz
Channel-to-Channel mismatch
Gain Phase
DC offset after calibration Wake-up time
1 See Analog input pin for definition of I/Q DAC output common-mode level.
3.4.3
RSSI ADC
Table 5. RSSI ADC Specifications
Parameter Condition -- -- -- -- -- Min -- 10 0 -- -- Typ 6 -- -- 3 1.0 Max -- -- 3 -- -- Units bit MHz V cycles LSB
RSSI ADC specifications are shown in Table 5.
Resolution Maximum Sampling Frequency Input Voltage Range Latency Integral Nonlinearity (INL)
LP1071 Advance Information, Rev. 0.5 8 PRELIMINARY Freescale Semiconductor
Functional Description
Table 5. RSSI ADC Specifications (continued)
Parameter Differential Nonlinearity (DNL) ENOB Fin = 100 kHz Condition -- Min -- -- Typ 0.5 5.5 Max -- -- Units LSB bit
3.4.4
Aux ADC
Table 6. Aux ADC Specifications
Parameter Condition -- -- -- -- -- -- Fin= 100 kHz Gain Phase Min -- 1 0 -- -- -- -- -- -- -- -- Typ 8 -- -- 9 1.0 0.5 7.2 0.2 0.5 -- -- Max -- -- AVdd -- -- -- -- -- -- 10 2 Units bit MHz V cycles LSB LSB bit dB Degree s s
Aux ADC specifications are shown in Table 6.
Resolution Maximum Sampling Rate Input Voltage Range Latency Integral Nonlinearity (INL) Differential Nonlinearity (DNL) ENOB Channel-to-Channel mismatch
Wake-up time
From Shutdown From Standby
3.4.5
Aux DAC
Table 7. Aux DAC Specifications
Parameter Condition -- -- input1 -- -- -- -- -- -- Min -- 20 0.1 5 10 -- -- -- -- 5 80 1.0 0.5 -- -- -- -- Typ 8 -- -- 2.4 Max -- Units bit MHz V kOhm pF ns ns LSB LSB
AUX DAC specifications are shown in Table 7.
Resolution Maximum Update rate Output voltage for full scale Load Propagation delay (tpd) Settling time (ts) Integral Nonlinearity (INL) Differential Nonlinearity (DNL)
LP1071 Advance Information, Rev. 0.5 Freescale Semiconductor PRELIMINARY 9
LP1071 Interfaces
Table 7. Aux DAC Specifications (continued)
Parameter ENOB Wake-up time Condition Fin= 1MHz From Shutdown From Standby Min -- -- -- Typ 7.2 -- -- Max -- 10 2 Units bit s s
1 Due to saturation of the output buffer, INL and DNL are not applicable for output voltages below 200 mV. Output is monotonic above 0.1 V.
4
4.1
LP1071 Interfaces
SDIO Host Interface
The LP1071 supports SDIO Card Specifications, Version 1.00 (http://www.sdcard.org). The LP1071 SDIO host interface supports the I/O mode of the SD Card Specifications.
4.1.1
SDIO Supported Features
The features supported by the LP1071 SDIO host interface are: * SD 1-Bit Mode * SD 4-Bit Mode * Low Speed * Full Speed (25 MHz) * Interrupt * CMD52 during Data Transfer * CMD53 Multi Block Transfer * Interrupt during 4-bit Multiple Block Data Transfer * Combo Card (I/O mode only)
4.1.2
SDIO Function 0/1
For Function 0 registers descriptions, refer to SDIO Card Specification. For Function 1, the SDIO registers occupy a 128 Kbyte space as defined in the SDIO specification. Figure 2 illustrates SDIO Function 1 128 Kbyte Memory Map and Table 8 details its registers.
LP1071 Advance Information, Rev. 0.5 10 PRELIMINARY Freescale Semiconductor
LP1071 Interfaces
Bit7 0x0000 Reserved
Bit0 0x0015 Reserved
0x0016 Reserved 0x0017 ARM to Host Interrupt Enable register 0 0x0018 ARM to Host Interrupt Enable register 1 0x001C SDIO Mailbox semaphore 0 0x001D SDIO Mailbox semaphore 1 0x001E SDIO Mailbox semaphore 2 0x0020 0x000E Watchdog Reset Register 0x000F SDIO Host to Device Interrupt Register 0 0x0010 0x0011 0x0012 0x0013 0x0014 Reserved Reserved Reserved ARM to Host Interrupt Source register 0 ARM to Host Interrupt Source register 1 0x27FF 0x2800 0x3FFF 0x4000 8Kbyte Internal Memory 0x5FFF
Figure 2. SDIO Function 1 128 Kbyte Memory Map
Reserved 2 KByte Mailbox space RAM0 RAM1 RAM2 Reserved 0x200E 0x200F 0x23FF 0x2400
0x1FFF 0x2000
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LP1071 Interfaces
Table 8. SDIO Function 1 Registers
Bit Name Description ARM Access HOST Access Reset
Watchdog Status Register (offset 0x000E) 0 Wdog_reset This is a read only bit that when `1' indicates that the LP1071 ASIC has had a watchdog reset occur. -- R R 0
7:1
Reserved
--
--
--
SDIO Host to Device Interrupt request register 0 (0x000F) 7:0 Write_sdio_arm_int Each bit in this register is 1 of 8 ARM interrupt requests from the SDIO Host to the device ARM. The Host should request an interrupt by writing a "1" to the corresponding bit in this register. The register will be read as a "1" until the ARM clears the register. Once the ARM has cleared the register then the corresponding bit will be read as "0" again. -- RW 0's
Device to SDIO Host Interrupt Source register 0 (0x0013) 7:0 Arm_to_sdio_int_clr[7:0] for writes. Arm_to_sdio_int_src[7:0] for reads. This register contains the interrupt pending status of the SDIO Host interrupt from the device. The device is capable of generating up to 8 individual requests. Each bit in this register is ANDed with the corresponding ARM to SDIO Host Interrupt enable register. The ANDed bits are then ORed together to generate a single SDIO Host interrupt in the cccr register space. To clear a particular interrupt bit the SDIO Host should write a "1" to that particular bit in this register. -- RW 0's
Device to SDIO Host Interrupt Source register 1 (0x0014) 2:0 Arm_to_sdio_int_clr[10:8] for This register contains the interrupt pending status writes. of the SDIO Host semaphore 0-2 host granted indication. When the Host requests a semaphore Arm_to_sdio_int_src[10:8] the corresponding interrupt will be triggered when for reads. the host has been granted the interrupt. Bit 0 is semaphore 0; bit 1 is semaphore 1; and bit 2 is semaphore 2. Each bit in this register is ANDed with the corresponding ARM to SDIO Host Interrupt enable register. The ANDed bits are then ORed together to generate a single SDIO Host interrupt in the cccr register space. To clear a particular interrupt bit the SDIO Host should write a "1" to that particular bit in this register. Reserved -- -- RW 0's
7:3
--
--
--
LP1071 Advance Information, Rev. 0.5 12 PRELIMINARY Freescale Semiconductor
LP1071 Interfaces
Table 8. SDIO Function 1 Registers (continued)
Bit Name Description ARM Access HOST Access Reset
Device to SDIO Host Interrupt Enable 0 (0x0017) 7:0 Arm_to_sdio_inte_en[7:0] Individual bit enables for each of the device to host interrupt source bits. Setting the corresponding bit to a "1" enables the interrupt; "0" disables the interrupt. The SDIO Host can disable all interrupts by disabling the main SDIO host interrupt in the CCCR register. -- RW 0's
Device to SDIO Host Interrupt Enable 1 (0x0018) 2:0 Arm_to_sdio_inte_en[10:8] Individual bit enables for each of the device to host interrupt source bits. Setting the corresponding bit to a "1" enables the interrupt; "0" disables the interrupt. The SDIO Host can disable all interrupts by disabling the main SDIO host interrupt in the CCCR register. Bit 0 is enable for semaphore 0 granted; bit 1 is semaphore 1; and bit 2 is semaphore 2. 7:3 -- Reserved -- -- -- -- RW 0's
SDIO Host Mailbox Semaphore 0 Register (offset 0x001C) 1:0 Sdio_mbxp_0_sema 2 bit semaphore register to control whether the host or the device has access to the shared mailbox ram 0. The host should write a "01" to this register to request the shared ram 0. After writing "01" the host should read this register. If the value is "01" then the host owns access to the mailbox. If the value read is "11" then the device owns access to the mailbox. When the host is done utilizing the mailbox then it should release ownership of the mailbox by writing "00" to this register. -- RW RW 0's
7:2
Reserved
--
--
--
SDIO Host Mailbox Semaphore 1 Register (offset 0x001D) 1:0 Sdio_mbxp_1_sema 2 bit semaphore register to control whether the host or the device has access to the shared mailbox ram 1. The host should write a "01" to this register to request the shared ram 1. After writing "01" the host should read this register. If the value is "01" then the host owns access to the mailbox. If the value read is "11" then the device owns access to the mailbox. When the host is done utilizing the mailbox then it should release ownership of the mailbox by writing "00" to this register. -- RW RW 0's
7:2
Reserved
--
--
--
LP1071 Advance Information, Rev. 0.5 Freescale Semiconductor PRELIMINARY 13
LP1071 Interfaces
Table 8. SDIO Function 1 Registers (continued)
Bit Name Description ARM Access HOST Access Reset
SDIO Host Mailbox Semaphore 2 Register (offset 0x001E) 1:0 Sdio_mbxp_2_sema 2 bit semaphore register to control whether the host or the device has access to the shared mailbox ram 2. The host should write a "01" to this register to request the shared ram 2. After writing "01" the host should read this register. If the value is "01" then the host owns access to the mailbox. If the value read is "11" then the device owns access to the mailbox. When the host is done utilizing the mailbox then it should release ownership of the mailbox by writing "00" to this register. -- RW RW 0's
7:2
Reserved
--
--
--
992 byte Mailbox RAM 1 (offset 0x200F to 0x23FF) 7:0 Mbox_rdata_1[15:0] Shared SDIO Mailbox. Both the ARM and Host can use the mailbox for message exchange between the SDIO device and the SDIO Host. Prior to accessing the SDIO Mailbox the Host should request and be granted the mailbox via the mailbox semaphore 1 register described above. Once the Host has been granted access to the mailbox it may read/write the mailbox however it likes. If the Host has not been granted access to the mailbox it will not be able to read or write the mailbox. Once the Host is finished with the mailbox it should release control of the mailbox as described in the mailbox semaphore 1 register. RW RW --
1 Kbyte Mailbox RAM 2 (offset 0x2400 to 0x27FF) 7:0 Mbox_rdata_2[15:0] Shared SDIO Mailbox. Both the ARM and Host can use the mailbox for message exchange between the SDIO device and the SDIO Host. Prior to accessing the SDIO Mailbox the Host should request and be granted the mailbox via the mailbox semaphore 2 register described above. Once the Host has been granted access to the mailbox it may read/write the mailbox however it likes. If the Host has not been granted access to the mailbox it will not be able to read or write the mailbox. Once the Host is finished with the mailbox it should release control of the mailbox as described in the mailbox semaphore 2 register. RW RW --
LP1071 Advance Information, Rev. 0.5 14 PRELIMINARY Freescale Semiconductor
Timers/Reset
Table 8. SDIO Function 1 Registers (continued)
Bit Name Description ARM Access HOST Access Reset
8 Kbyte Internal Memory Buffer RAM (offset 0x4000 to 0x5FFF) 7:0 Imem_rdat[15:0] This is an internal memory buffer for specific use by the SDIO device. Data is read or written to this memory via SDIO cmd 53 reads or writes. Then, the SDIO DMA controller is used to move the data from the internal memory buffer to/from shared memory under device (ARM) control. -- RW --
4.2
4.2.1
*
RF Interface
Serial Programmable Interface (SPI)
The SPI is composed of 3 signals: 1. RF_SIF_0_SCLK (serial clock) 2. RF_SIF_1_CS_N (chip select) 3. RF_SIF_2_DIN (data input) The serial information is sent to the RF transceiver in 18 bit bursts framed by chip select. The 18 bits comprises of leading 14 (or less) data bits and trailing 4 address bits Programming clock edges are ignored until chip select goes active low. All bits are shifted in on the rising edge of the clock and latched in when chip select returns inactive high. (permissible for the clock in either state) The interface can be programmed in any operating mode. Serial information is clocked in with the most significant bit (MSB) first. The address bits for the internal registers are decoded on the rising edge of chip select. The rising edge of chip select initiates an internal parallel load pulse that latches the last 18-bit serially shifted-in data into the internal register.
* * * * * * *
5
Timers/Reset
The TCXO generates the 40 MHz RFIC 800 mV clipped sine wave reference clock. The TCXO output is converted to a digital signal via a clock squarer input pad circuit. The 40 MHz TCXO reference is used to generate the 40 MHz IQDAC clock and the 20 MHz IQADC clock. The PLL synthesizes a reference from the 40 MHz reference. The reference is then used to generate the BRC, ARM, PAS and Symbol Processor clocks, the 44 MHz IQ DAC clock and the 22 MHz IQ ADC clock. When the TCXO and PLL are powered down the only active clock source is the 32 kHz XTAL, a.k.a. the Slow Clock. The TCXO, PLL and XTAL clock references all include bypass MUXes which allow the individual clock reference to be driven by an external signal. Figure 3 illustrates the high level clocking of the LP1071 with the associated pins.
LP1071 Advance Information, Rev. 0.5 Freescale Semiconductor PRELIMINARY 15
Pinout and Footprint
Chip Boundary
PLL_BYPAS S PLL_BYPASS_CLK
40 MHz
88 MHz TCXO_BYPASS TCXO_BYPASS_CLK
ARM
TCXO
40 MHz
PLL
Clock Control Cuircuits
44 MHz 20 MHz 22 MHz
AFE
FAST_CLK_PWR XTAL_BYPASS XTAL_BYPASS_CLK 32 kHz
XTAL
32 kHz
Figure 3. LP1071 Clocks
5.1
System Clock
The LP1071 is clocked using an external crystal oscillator (XO) or a temperature compensated crystal oscillator (TCXO) running at 40MHz with a frequency resolution of 20 ppm or better.
5.2
PLL Block
PLL Bypass
5.3
Low Frequency Clock
The LP1071 uses a low power 32 kHz crystal oscillator to maintain the timing during sleep.
6
6.1
Pinout and Footprint
Pinout
Table 9. Pin Description
Pad Name Pad Type Direction Description Pin
See Table 9 for the pin description.
Power and Ground Pads VDD_IO pvdd2dgz N/A 3.3 V I/O power pad (22 mA per pad max current) K1
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Pinout and Footprint
Table 9. Pin Description (continued)
Pad Name VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VSS_IO VSS_IO VSS_IO VSS_IO VSS_IO VSS_IO VSS_IO VSS_IO VDD_CORE VDD_CORE VDD_CORE VDD_CORE VDD_CORE VDD_CORE VSS_CORE VSS_CORE VSS_CORE VSS_CORE VSS_CORE VSS_CORE Pad Type pvdd2dgz pvdd2dgz pvdd2dgz pvdd2dgz pvdd2dgz pvss2dgz pvss2dgz pvss2dgz pvss2dgz pvss2dgz pvss2dgz pvss2dgz pvss2dgz pvdd1dgz pvdd1dgz pvdd1dgz pvdd1dgz pvdd1dgz pvdd1dgz pvss1dgz pvss1dgz pvss1dgz pvss1dgz pvss1dgz pvss1dgz Direction N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A Description 3.3 V I/O power pad (22 mA per pad max current) 3.3 V I/O power pad (22 mA per pad max current) 3.3 V I/O power pad (22 mA per pad max current) 3.3 V I/O power pad (22 mA per pad max current) 3.3 V I/O power pad (22 mA per pad max current) I/O ground pad (94 mA max current) I/O ground pad (94 mA max current) I/O ground pad (94 mA max current) I/O ground pad (94 mA max current) I/O ground pad (94 mA max current) I/O ground pad (94 mA max current) I/O ground pad (94 mA max current) I/O ground pad (94 mA max current) 1.8 V core power pad (31 mA per pad max current) 1.8 V core power pad (31 mA per pad max current) 1.8 V core power pad (31 mA per pad max current) 1.8 V core power pad (31 mA per pad max current) 1.8 V core power pad (31 mA per pad max current) 1.8 V core power pad (31 mA per pad max current) core ground pad (25 mA per pad max current) core ground pad (25 mA per pad max current) core ground pad (25 mA per pad max current) core ground pad (25 mA per pad max current) core ground pad (25 mA per pad max current) core ground pad (25 mA per pad max current) Pin L2 M5 K10 M11 C11 H4 J4 J6 J9 H8 H9 F9 E9 G1 M7 L11 G12 D9 A12 G4 J7 J8 G9 D8
LP1071 Advance Information, Rev. 0.5 Freescale Semiconductor PRELIMINARY 17
Pinout and Footprint
Table 9. Pin Description (continued)
Pad Name Clocks and Resets and Mode EMBEDDED_RESET_N PLL_BYPASS PLL_BYPASS_CLK AVDD_PLL AVSS_PLL TAVDDPOWER TAVssPOWER DVDD_PLL DVSS_PLL TXCO_BYPASS TXCO_BYPASS_CLK XTAL_BYPASS XTAL_BYPASS_CLK FAST_CLK_POWER XTAL_32K_XIN XTAL_32K_XOUT RESET_N CHIP_MODE0 CHIP_MODE1 CHIP_MODE2 CHIP_MODE3 JTAG JTAG_RESET JTAG_CLOCK JTAG_DI JTAG_DO JTAG_MODE ARM Sub-system Signals ARM_GPIO0 ARM_GPIO1 ARM_GPIO2 ARM_GPIO3 pdb04dgz pdb04dgz pdb04dgz pdb04dgz bi-dir bi-dir bi-dir bi-dir General Purpose I/O General Purpose I/O General Purpose I/O General Purpose I/O M2 L3 K4 L4 pdudgz pdisdgz pdudgz pdo02cdg pdudgz Input input input output input Tap reset Tap clock Tap data in Tap data out Tap Mode L7 L8 M8 K8 K9 pdisdgz pdidgz pdidgz pdidgz pdidgz pdisdgz pdidgz pdidgz pdiana2p pdiana2p pvdd3p pvss3p pdiana2p pdiana2p pdidgz pdidgz pdidgz pdidgz pdo02cdg pdxoe4dg input input input N/A N/A N/A N/A N/A N/A input input input input output analog analog Input Input Input Input Input Embedded board reset Bypass the internal PLL and use PLL_BYPASS_CLK PLL bypass clock input Analog 3.3 volt Analog ground 3.3 volt power for ESD Diodes 3.3 volt power for ESD Diodes 1.8 volt digital power for PLL 1.8 volt digital ground for PLL Bypass the TCXO and use the TCXO_BYPASS_CLK TCXO bypass clock Bypass the XTAL oscillator and use the XTAL_BYPASS_CLK XTAL bypass clock Enable the TCXO 32 kHz crystal (NOTE: Must be placed next to PVDD1DGZ.) 32 kHz crystal Chip Reset Chip Mode Select Chip Mode Select Chip Mode Select Chip Mode Select E10 A9 A10 D2 D1 E3 A3 F3 E2 B10 A11 D11 C12 B9 B12 B11 D10 G3 H2 H1 H3 Pad Type Direction Description Pin
LP1071 Advance Information, Rev. 0.5 18 PRELIMINARY Freescale Semiconductor
Pinout and Footprint
Table 9. Pin Description (continued)
Pad Name ARM_GPIO4 ARM_GPIO5 ARM_GPIO6 ARM_GPIO7 ARM_UART_0_DI ARM_UART_0_DO ARM_EEPROM_DAT_GPIO Pad Type pdb04dgz pdb04dgz pdb04dgz pdb04dgz pdb04dgz pdb04dgz pdb04dgz Direction bi-dir bi-dir bi-dir bi-dir Input output bi-dir bi-dir Description General Purpose I/O General Purpose I/O General Purpose I/O General Purpose I/O UART input data. UART output data. General Purpose I/O dedicated for EEPROM. General Purpose I/O dedicated for EEPROM. Pin M3 M4 K5 L5 K6 M6 L6 K7
ARM_EEPROM_CLK_GPIO pdb04dgz
SDIO Signals (other signals on interface are 1 Vdd and 2 Vss pins) CD/DAT3 (connector pin 1) DAT[2] (connector pin 9) DAT[1] (connector pin 8) DAT[0] (connector pin 7) CMD (connector pin 2) CLK (connector pin 5) AFE Interface AGND AGNDIQADC AGNDIQDAC_1 AGNDREF AVDD AVDDIQADC AVDDIQDAC_1 VDDIQADC VSSIQADC VDDIQDAC DGND DVDD IBIAS VBG VREFN VREFP AUXADCIN_0 pdiana2p pdiana2p pdiana2p pdiana2p pdiana2p pdiana2p pdiana2p pvdd3p pvss3p pvdd3p pvss1dgz pvdd1dgz pdiana2p pdiana2p pdiana2p pdiana2p pdiana2p N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A input input input Analog ground Analog ground Analog ground Analog Reference negative supply Analog 3.3 volt Analog 3.3 volt Analog 3.3 volt 3.3 volt power for ESD Diodes 3.3 volt ground for ESD Diodes 3.3 volt power for ESD Diodes Digital Ground Digital 1.8 Volt Pin for monitoring or bypassing bias current, flowing out of the pin to agnd. Voltage reference pin for decoupling (equal to 1.25 V). Connect 1 uF (ceramic) + 100 nF (ceramic) to agndref. ADC Negative reference for decoupling ADC Positive reference for decoupling Muxed analog input to auxiliary ADC bit 0 B3 A5 B7 B4 C1 F4 E4 B1 A1 C4 A4 C6 D4 D6 D7 A6 pduw04dgz pdu04dgz pdu04dgz pdu04dgz pdu04dgz pdisdgz bi-dir bi-dir bi-dir bi-dir bi-dir input card detect/data 3. data 2. data 1/interrupt. data 0/busy indication. command/response. clock J1 J2 J3 K2 K3 L1
LP1071 Advance Information, Rev. 0.5 Freescale Semiconductor PRELIMINARY 19
Pinout and Footprint
Table 9. Pin Description (continued)
Pad Name AUXADCIN_1 AUXADCIN_2 IADCINN IADCINP QADCINN QADCINP RSSIADCIN VOCM AUXDACOUT IDACOUTP IDACOUTN QDACOUTP QDACOUTN EXT_BIAS TCXO Squarer AVDD_TCXO AVSS_TCXO CLKIN RF Interface Signals RF_ANALOG_LDO RF_EN RF_RXEN RF_TXEN RF_PAEN1 RF_PAEN2 RF_SPARE1 RF_VGA6 RF_VGA5 RF_VGA4 RF_VGA3 RF_VGA2 RF_VGA1 RF_VGA0 pdb04dgz pdb04dgz pdb04dgz pdb04dgz pdb04dgz pdb04dgz pdb04dgz pdb04dgz pdb04dgz pdb04dgz pdo02cdg pdo02cdg pdo02cdg pdo02cdg bi-dir bi-dir bi-dir bi-dir bi-dir bi-dir bi-dir bi-dir bi-dir bi-dir output output output output LDO enable for RF VCO power. Driven by PHY controller. RF enable. Driven by PHY controller. RF Rx enable. Driven by PHY controller. RF Tx enable. Driven by PHY controller. RF PA enable 1. Driven by PHY controller. RF PA enable 2. Driven by PHY controller. RF spare 1 (not used). Driven by PHY controller. RF VGA setting. Driven by UWA RF VGA setting. Driven by UWA. RF VGA setting. Driven by UWA. RF VGA setting. Driven by UWA. RF VGA setting. Driven by UWA. RF VGA setting. Driven by UWA. RF VGA setting. Driven by UWA. L9 L10 M9 M10 L12 K11 J10 K12 J12 J11 H12 H10 H11 G10 pvdd3p pvss3p pdiana2p N/A N/A input Analog 3.3 volt Analog ground TCXO reference clock input F1 G2 F2 Pad Type pdiana2p pdiana2p pdiana2p pdiana2p pdiana2p pdiana2p pdiana2p pdiana2p pdiana2p pdiana2p pdiana2p pdiana2p pdiana2p pdiana2p Direction input input input input input input input input output output output output output input Description Muxed analog input to auxiliary ADC bit 1 Muxed analog input to auxiliary ADC bit 2 Negative input of I-ADC Positive input of I-ADC Negative input of Q-ADC Positive input of Q-ADC RSSI ADC input Input pin for definition of IQDAC output common-mode level Auxiliary DAC output Positive output of I-DAC Negative output of I-DAC Positive output of Q-DAC Negative output of Q-DAC External Bias for test Pin C3 A2 C7 B6 C5 D5 C2 B8 B2 C8 A7 A8 C9 D3
LP1071 Advance Information, Rev. 0.5 20 PRELIMINARY Freescale Semiconductor
Pinout and Footprint
Table 9. Pin Description (continued)
Pad Name RF_RXHP RF_ANTENNA_SEL RF_ANTENNA_SEL_N RF_SIF_2_DIN RF_SIF_1_CS_N RF_SIF_0_SCLK RF_LOCK_DETECT Pad Type pdo02cdg pdo02cdg pdo02cdg pdo02cdg pdo02cdg pdo02cdg pdidgz Direction output output output output output output input Description RF Rx highpass filter setting. Driven by UWA. RF antenna select. Driven by ARM. RF antenna select. Driven by ARM. RF 3-wire serial interface. Driven by ARM. RF 3-wire serial interface. Driven by ARM. RF 3-wire serial interface. Driven by ARM. RF lock detect. Read by ARM. Pin F12 G11 F10 F11 E11 E12 D12
6.2
pdisdgz pdidgz pdudgz pdusdgz pdddgz
Pad Descriptions
32 kHz crystal pad (1 pad w/2 pad connections) Schmitt triggered input 5 Volt tolerant 5 Volt tolerant input pad 5 Volt tolerant input pad w/internal pullup Schmitt Trigger Input Pad, 5V-Tolerant w/pullup Input Pad With Pulldown, 5-VT IO cmos 2 mA output cmos 4 mA output CMOS 3 state output pad w/input (5 volt tolerant) CMOS 3 state output pad w/input (5 volt tolerant) CMOS 3-State Output Pad with Schmitt Trigger Input and Pullup, 5V-Tolerant CMOS 3-State Output Pad with Input and Pulldown, 5V-Tolerant CMOS 3-State Output Pad with Input and Pulldown, 5V-Tolerant CMOS 3-State Output Pad with Input and Pulldown, 5V-Tolerant CMOS 3-State Output Pad, 5V-Tolerant CMOS 3-State Output Pad with Input and Pullup, 5V-Tolerant 3-State Output Pad with Input and Enable Controlled Pull-Up, 5V-Tolerant Low Frequency Analog I/O for use with power cut diodes (Note: It is recommended to utilize the secondary ESD protection circuit: ESND on these pads.
pdxoe4dg
pdo02cdg pdo04cdg pdb04dgz pdb02dgz pdu02sdgz pdd04dgz pdd04dgz pdd08dgz pdt04dgz pdu02dgz pduw02dgz pdiana2p
LP1071 Advance Information, Rev. 0.5 Freescale Semiconductor PRELIMINARY 21
DC Electrical Specifications
6.3
1 A IBIAS
Footprint
2 AUXADCIN_2 3 PVSS3P_2 4 VREFN 5 6 7 8 9 PLL_ BYPASS 10 PLL_ BYPASS_ CLK 11 TCXO_ CLK XTAL_ 32K_ XOUT XTAL_ 32K_XIN 12 VDD_ AVDDIQADC AGNDIQDAC_ IDACOUTN QDACOUTP 1
BYPASS_ CORE_5
B
DVDD
AUXDACOUT
AVDD
PVDD3P_2
NC
IADCINP
AVDDIQDAC _1
VOCM
FAST_CLK_ POWER
TCXO_ BYPASS
C
PVSS3P_1
RSSIADCIN
AUXADCIN_1
VBG
QADCINN
VREFP
IADCINN
IDACOUTP QDACOUTN
NC
VDD_ IO_6
XTAL_ BYPASS _CLK
D
AVSS_PLL
AVDD_PLL
EXT_BIAS
AUXADCIN_ 0
QADCINP
AGND
AGNDIQADC
GND
GND
RESET_N
XTAL_ BYPASS
RF_ LOCK_ DETECT
E TAVSSPOWER DVSS_PLL
TAVDDPOWER
DGND
GND
GND
GND
GND
GND
EMBEDDED RF_SIF_ _RESET_N
RF_ CLK
1_CS_N SIF_0_S
F
AVDD_ TCXO
CLKIN
DVDD_PLL
PVDD3P_1
GND
GND
GND
GND
GND
RF_ ANTENNA_ SEL_N
RF_SIF_ 2_DIN
RF_ RXHP
G
VDD_ CORE_1
AVSS_ TCXO
CHIP_ MODE_0
GND
GND
GND
GND
GND
GND
RF_VGA_0
RF_ _SEL
VDD_
ANTENNA CORE_4
H
CHIP_ MODE_2
CHIP_ MODE_1 SD_DAT_2
CHIP_ MODE_3 SD_DAT_1
GND
GND
GND
GND
GND
GND
RF_VGA_2 RF_VGA_ 1
RF_ VGA_3 RF_ VGA_5 RF_ VGA_6
J
SD_DAT_3
GND
GND
GND
GND
GND
GND
RF_ SPARE1
RF_VGA_ 4 RF_ PAEN2
K
VDD_IO_1
SD_DAT_0
SD_CMD
ARM_ GPIO_2
ARM_ GPIO_6
ARM_ UART_0_DI
ARM_ EEPROM_ CLK_GPIO
JTAG_DO
JTAG_ MODE
VDD_IO_4
L
SD_CLK
VDD_IO_2
ARM_ GPIO_1
ARM_ GPIO_3
ARM_ GPIO_7
ARM_ EEPROM_ DAT_GPIO
JTAG_ RESET
JTAG_ CLOCK
RF_ ANALOG_ LDO
RF_EN
VDD_ CORE_3
RF_ PAEN1
M
VDD_IO_2
ARM_ GPIO_0
ARM_ GPIO_4
ARM_ GPIO_5
VDD_IO_3
ARM_ UART_0_ DO
VDD_ CORE_2
JTAG_DI
RF_RXEN
RF_TXEN
VDD_IO_ 5
VDD_ CORE_3
7
7.1
DC Electrical Specifications
Absolute Maximum Ratings
Absolute maximum ratings are shown in Table 10.
LP1071 Advance Information, Rev. 0.5 22 PRELIMINARY Freescale Semiconductor
DC Electrical Specifications
Table 10. Absolute Maximum Ratings
Parameter Supply Voltage (3.0 V) Supply Voltage (1.8 V) Input Voltage DC Output Current Storage Temperature Electrostatic Discharge Voltage Min -0.3 -0.3 GND - 0.3 TBD TBD TBD Max 4.0 2.2 VDD + 0.3 TBD TBD TBD Units V V V mA
o
C
V
Operating the LP1071 under conditions that exceed Absolute Maximum Ratings may result in permanent damage to the device. Absolute maximum ratings are limiting values, and are considered individually, while all other parameters are within their specified operating ranges.
7.2
Recommended Operating Conditions
Table 11. Recommended Operating Conditions
Parameter Supply I/O Voltage Supply Core Voltage Operating Temperature Symbol VDD_IO VDD_C TA Min 3.0 1.71 0 Max 3.6 1.89 70 Units V V
oC
Recommended operating conditions are shown in Table 11.
Thermal dissipation (for multi-layer PCB) is shown in Table 12.
Table 12. Thermal Dissipation (for multi-layer PCB)
# PCB Layers # PCB Vias PCB Trace Density JEDEC JEDEC 6% JA (C/W) 0 m/s 96.1 81.7 66.9 1 m/s 68.9 60.2 51.3 2 m/s 59.6 52.6 45.8 JT (C/W) 1.0 0.9 0.7 JC (C/W) 6.5 6.2 6.0
1 (1s) 2 (2s)
0 36 0
7.3
DC Characteristics
Table 13. DC Characteristics
Parameter Symbol VDD VD33 Condition -- -- Min 1.62 3.0 Typ 1.8 3.3 Max 1.98 3.6 Units V V
DC characteristics are shown in Table 13.
Pre-driver Supply Voltage I/O Supply Voltage
LP1071 Advance Information, Rev. 0.5 Freescale Semiconductor PRELIMINARY 23
DC Electrical Specifications
Table 13. DC Characteristics (continued)
Parameter Low-level input voltage High-level input voltage Threshold point Schmitt Trigger Low to High Thresh Schmitt Trigger High to Low Thresh Input Leakage Current 3-state leak current Symbol VIL VIH VT VT+ VTII IOZ Schmitt Schmitt VI =VD33 or 0V VOH = VSS VOL = VDD Output low voltage Output high voltage Low Level Out Current @VOL=0.4V VOL VOH IOL IOL = 2,4,..., 24mA IOH =2,4,..., 24mA 2 mA 4 mA 8 mA 12 mA 16 mA 24 mA High Level Out Current @VOH=2.4V IOH 2 mA 4 mA 8 mA 12 mA 16 mA 24 mA Condition -- -- -- Min -0.3 2.0 1.46 1.47 0.90 -10 -10 -10 -- 2.4 2.2 4.5 TBA 1 TBA 2 TBA TBA 12.3 18.5 22.7 36.9 Typ -- -- 1.58 1.50 0.94 -- -- -- -- -- 3.3 6.6 TBA 19.7 TBA 39.5 TBA TBA 24.8 37.1 49.5 74.3 Max 0.8 5.5 1.75 1.50 0.96 10 10 10 0.4 -- 3.8 7.6 TBA 22.7 TBA 45.4 TBA TBA 38 56.9 75.9 113.9 Units V V V V V A A A V V mA mA mA mA mA mA mA mA mA mA mA mA
LP1071 Advance Information, Rev. 0.5 24 PRELIMINARY Freescale Semiconductor
Timing Characteristics
8
8.1
8.1.1
Timing Characteristics
AFE Interface
I/Q ADC
Figure 4. Timing of the Pipelining Operation in I/Q ADC
8.1.2
I/Q DAC
Figure 5. Timing Diagram of the I/Q DAC Inputs and Outputs
LP1071 Advance Information, Rev. 0.5 Freescale Semiconductor PRELIMINARY 25
Timing Characteristics
8.1.3
RSSI ADC
Figure 6. Timing of the RSSI ADC Pipelining Operation
8.1.4
Auxiliary ADC
Figure 7. Timing of the Aux ADC Successive Approximation Operation
LP1071 Advance Information, Rev. 0.5 26 PRELIMINARY Freescale Semiconductor
Timing Characteristics
8.1.5
Auxiliary DAC
Figure 8. Conversion Cycle in Normal Operation for Aux DAC Table 14. Aux DAC Timing Parameters
Symbol tpd ts Parameter Propagation delay Settling time Min -- -- Typ 5 80 Max -- -- Units ns ns
LP1071 Advance Information, Rev. 0.5 Freescale Semiconductor PRELIMINARY 27
Mechanical Dimensions
9
Mechanical Dimensions
The LP1071 is a 144-pin Very-thin Fine-pitch Ball Grid Array (VFBGA) package. All dimensions are mm.
Figure 9. LP1071 Package
10 Development Support
In addition to the LP1071 baseband and MAC, Freescale provides developers with reference designs, development platform, software drivers, system development software, testing and debugging tools and a full set of technical documentation that includes: * User Guide * Data Sheet * Schematics * Gerber Files * Application Notes Freescale also provides multi-interface reference designs to aid device manufacturers with today's demanding time-to-market requirements.
LP1071 Advance Information, Rev. 0.5 28 PRELIMINARY Freescale Semiconductor
Appendix: Comparison of LP1071 and LP1072
11 Appendix: Comparison of LP1071 and LP1072
Table 15. Comparison of LP1071 and LP1072
Item Network Standard Support Network Architectures Data Rates LP1071 IEEE 802.11 a/b/g Infrastructure, AdHoc 802.11 a/g: 6, 9, 12, 18, 24, 36, 48, 54 Mbps 802.11b: Modulation Techniques Security Receiver Sensitivity1 802.11g 6 Mbps: 9 Mbps: -91.0 dBm -90.5 dBm 1, 2, 5.5, 11 Mbps LP1072
BPSK, QPSK, 16QAM, 64QAM, CCK, OFDM, DSSS 40- and 128-bit WEP, TKIP, WPA, AES 802.11b 1 Mbps: 2 Mbps: -97.4 dBm -94.1 dBm
12 Mbps: -88.6 dBm 18 Mbps: -86.4 dBm 24 Mbps: -81.4 dBm 36 Mbps: -79.9 dBm 48 Mbps: -76.1 dBm 54Mbps: -73.1 dBm Power Consumption
5.5Mbps: -92.5 dBm 11Mbps: -88.9 dBm
Receive: 150 mW avg (@54Mbps) Listen: Sleep: 132 mW Less than 1 mW 3.0 - 3.6 Vdc
Supply Voltage
I/O:
Core: 1.8 5% Vdc Operating Temperature Host Interface SDIO 0 oC to +70 oC; < 95% humidity SDIO CompactFlash Plus (CF+) Other Interfaces Operating System Support Package Semiconductor Technology RF Support Reference Designs Certification 1 Using Maxim RF SDIO JTAG, 8 GPIOs, 1 UART, Serial / EEPROM Microsoft Windows CE.net 3.0 and 4.2, 5.0 Microsoft Pocket PC 2002, 2003 144-pin VFBGA, 9 x 9 x 1.0 mm 200-pin VFBGA, 13 x 13 x 1.0 mm
0.18 micron Airoha, Maxim CF+ Wi-Fi (incl. WPA), WHQL, FCC Part 15
LP1071 Advance Information, Rev. 0.5 Freescale Semiconductor PRELIMINARY 29
Revision History
12 Revision History
This document's updated format reflects that Freescale Semiconductor, Inc. acquired CommASIC on October 20, 2005. Since the release of the previous version of this document (Rev. 0.4), the technical content has not been updated.
LP1071 Advance Information, Rev. 0.5 30 PRELIMINARY Freescale Semiconductor
NOTES
LP1071 Advance Information, Rev. 0.5 Freescale Semiconductor PRELIMINARY 31
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Document Number: LP1071 Rev. 0.5 12/2005
PRELIMINARY

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